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JetXTS

High Speed XTS-AES Core

Overview

The IEEE draft P1619 specifies the XTS-AES mode (XEX-based Tweaked codebook mode with ciphertext Stealing) of AES operation to provide encryption of storage at the sector level. The AES disk encryption algorithm utilizes a Galois field multiplication, and a pair of keys – an AES key and a tweak key. This recent IEEE draft replaces the previous draft LRW-AES (Lislov, Rivest and Wagner) mode.

The JetXTStm Fast is optimized for IEEE P1619 applications. It integrates an optimized Galois Field Multiplier with a high performance fully verified JetAEStm cryptographic core. It supports ciphertext stealing for any disk with sector size not divisible by 128. The core performs both encryption and decryption using 128+128 and 256+256 bit key sizes according to the P1619 draft. Its design is fully synchronous for portability. The core is available for licensing in both source and netlist form.

Features

Ø        Fully compliant with XTS-AES mode as specified in IEEE draft P1619

Ø        Two cores

·     JetXTStm Fast - Throughput up to 3 Gbps

·     JetXTStm Ultra Fast - Throughput up to 50 Gbps

Ø        Simple interface

Ø        Fully synchronous design

Ø        Flow-through design

Ø        Support 128-bit or 256-bit AES key size and 128-bit or 256-bit tweak key size as defined in P1619

Ø        Support CTS (Cipher Text Stealing) for sector size not divisible by 128

Ø        On-the-fly hardware key expansion

Ø        Key expansion can also be performed in software to reduced the gate count

Ø        Core is available as a synthesizable Verilog source code, or as a netlist

Ø        Self-checking test bench

Application

Ø        IEEE P1619 hard disk encryption applications

Core I/O

For more details, see datasheet.

Deliverables

The core is available in soft IP form, either as a Netlist or HDL Source.  The deliverables include:

·          For   Netlist Licenses :             Target specific net list

·          For   HDL Licenses :                 Fully synthesizable RTL Verilog source

·          Self-checking test bench

·          Simulation script, test vectors and expected results

·          User documentation

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More Information

For more detailed information on this or any of our other products and services, please contact us and we will be pleased to discuss how we can assist with your individual requirements.

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www.security-cores.com

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www.jetsmt.com


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