Overview

The JetCombo^tm-1 core implements both the AES-GCM (Galois Counter Mode) and AES-CCM (Counter with CBC-MAC) to provide authentication and privacy.  Typical applications of the core are high-speed network security and storage data protection.

JetCombo^tm–1 core integrates a Galois Field Multiplier, a high performance fully verified JetAES^tm cryptographic core in counter mode and CBC-MAC mode to provide authenticated encryption.  The cores support encryption, decryption, authentication, and verification functionalities for both GCM and CCM modes and can be used with 128-bit, 192-bit, and 256-bit key sizes.  The cores are available for licensing in both source and netlist form.

Features

Ø        Fully compliant with both AES-GCM and AES-CCM modes as specified in

·         IEEE standard 802.1ae

·         Wireless security standards

·         Fibre Channel Security Protocol

·         IETF RFC-4106, RFC4309

·         IEEE draft standard P1619.1

Ø        Simple interface

Ø        Fully synchronous design

Ø        Flow-through design

Ø        Throughput up to 3 Gbps

Ø        Combine both AES-GCM/CCM encryption--authentication and decryption-verification

Ø        Support 128-bit, 192-bit or 256-bit key sizes

Ø        On-the-fly hardware key expansion

Ø        Key expansion can also be done in software to reduce gate count

Ø        Available as synthesizable Verilog source code, or as a netlist

Ø        Self-checking test bench

Applications

Ø        IPsec, Virtual Private Networks (VPN)

Ø        Wireless network security

Ø        Security in data storage  (IEEE P1619.1)

Ø        Storage Area Networks (SAN)

Ø        Optical transmission networks

Ø        Voice over IP (VoIP)

Ø        MACsec Ethernet security (IEEE 802.1ae)

Core I/O

For more details, see datasheet.

Deliverables

The core is available in soft IP form, either as a Netlist or HDL Source.  The deliverables include:

·          For   Netlist Licenses :             Target specific net list

·          For   HDL Licenses :                 Fully synthesizable RTL Verilog source

·          Self-checking test bench

·          Simulation script, test vectors and expected results

·          User documentation

Export Permits

More Information

For more detailed information on this or any of our other products and services, please contact us and we will be pleased to discuss how we can assist with your individual requirements.

request information www.security-cores.com or www.jetsmt.com