Overview

The JetAES^tm Fast encryption and decryption IP cores implement the AES (Rijndael) encryption standard, as described in the NIST Federal Information Processing Standard (FIPS) 197.

The cores are designed to be highly flexible and can be integrated into any AES design with ease. Different options are available for achieving the best speed/area results for specific applications. The cores support both encryption and decryption functionality and can be used with all or any of the three AES key sizes (128, 192, 256-bit).  The cores are available for licensing in both source and netlist form.

Features

Ø        Fully compliant with AES described in NIST FIPS 197

Ø        Simple interface

Ø        Fully synchronous design

Ø        Flow-through design

Ø        Fast Version

     • 128-bit wide data path

     • Throughput up to 3 Gbps

Ø        Fast- Double Speed Version

     • Pipelined 128-bit wide data path

     • Throughput up to 6 Gbps

Ø        128-bit wide data path processes each round in single clock cycle 

Ø        User programmable key size of 128, 192 or 256-bit change dynamically

Ø        Cores with lower gate count are also available for specific key size

Ø        Building block for ultra-high throughput solution

Ø        On-the-fly hardware key expansion

Ø        No dead cycle when changing keys

Ø        Key expansion can also be performed in software to reduced the gate count

Ø        Separate cores for encryption and decryption

Ø        Combined encryption-decryption core also available with minimum gate count

Ø        Supports ECB mode.  Optional wrapper is included to support all AES classic block cipher modes like CBC, CFB, OFB or CTR

Ø        Available solutions for more advanced “modes” of AES, such as AES-CCM, AES-GCM, LRW-AES

Ø        Core is available as a synthesizable Verilog source code, or as a netlist

Ø        Self-checking test bench with FIPS test vectors

Applications

Ø        Security in networked environments

     • IPsec, SSL, Virtual Private Networks (VPN)

     • Storage Area Networks (SAN)

     • Optical transmission networks

     • Voice over IP (VoIP)

     • MACsec Ethernet security (IEEE 802.1ae)

Ø        Security in program content

Ø        Security in electronic financial transactions

Ø        Security in video surveillance systems

Ø        Security in military communications systems

Ø        Security in audio communications

Ø        Security in data storage

Block Diagram

Core I/O

For more details, see datasheet.

Deliverables

The core is available in soft IP form, either as a Netlist or HDL Source.  The deliverables include:

·          For   Netlist Licenses :             Target specific net list

·          For   HDL Licenses :                 Fully synthesizable RTL Verilog source

·          Self-checking test bench

·          Simulation script, test vectors and expected results

·          User documentation

Export Permits

More Information

For more detailed information on this or any of our other products and services, please contact us and we will be pleased to discuss how we can assist with your individual requirements.

request information www.security-cores.com or www.jetsmt.com